Heterogeneous Integration Versus Dimensional Scaling; One Year In (Part 2)

In the first part of this series, I covered the perspectives of dimensional scaling vs. heterogeneous integration based on discussions during SEMICON West 2017. For part two, I spoke with equipment and material suppliers who serve either (or in some cases, both) the front- and back-ends of the semiconductor manufacturing industry, to round out the picture of how the industry-wide shift in focus from scaling to the heterogeneous integration roadmap is impacting them.

To set the stage, consider that there are four companies with pockets that are deep enough to continue dimensional scaling efforts down to 3nm nodes: Intel, TSMC, Samsung, and GLOBALFOUNDRIES. Even then, in the past few years, they have all recognized the value of heterogeneous integration enabled by advanced wafer level packaging and 3D integration technologies and invested in adding those capabilities to their portfolios. Additionally, integrated device manufacturers (IDMs) like Intel are developing packaging technologies, as well as original equipment manufacturers (OEMs), like Samsung.

In a Nutshell
Entegris, traditionally a front-end company focused on developing products that purify, protect, and transport critical materials used in semiconductor manufacturing, has extended efforts in the past 12-18 months beyond front-end applications to include heterogeneous integration technologies. memsstar, a company that specializes in refurbished tools for the semiconductor market as well as new tools designed for MEMS processing, reports that it won’t be greatly impacted, as the transition will take time, and the company serves both markets. Manufacturers of electronic performance materials, like Brewer Science and Merck, are now emphasizing development in advanced packaging materials while still maintaining their lithography materials for front-end technologies. Then there’s Reno Sub-Systems, a two-year old start up whose plasma ignition subsystem for plasma deposition tools are targeted towards enabling future nodes, and sees ample opportunity from the four companies who will continue scaling efforts. Lastly, there are companies like Invensas, a subsidiary of Xperi; EV Group, UnItySC, and Ultratech, a division of Veeco, who saw the writing on the wall 10 years ago and have been focused on advanced wafer level packaging and 3D Integration ever since. They are particularly excited about what this means for them.

The Dimensional Scaling Debate
“People are creatures of habit and have always wanted to just scale further. The back-end got left behind,” explained Rico Wiedenbruch, Merck. “However, as scaling becomes more complicated and expensive, the industry has turned to the back-end to improve communication between the processor and the memory.”

“Scaling will always be there until we get to 3nm,” said Tony McKie, memsstar. “The problem with scaling is that there are only a few companies who can do it. The price of the tools is phenomenal.”

Additionally, McKie explained that as scaling continues, the device wafers that MEMS are built on top of becomes more and more expensive. MEMS equipment, therefore, can have a negative impact on the device wafer. Therefore, it’s more critical than ever that the equipment manufacturers provide tools that feature repeatability and reliability.

Wiedenbruch holds the huge delay in extreme ultra violet (EUV) lithography responsible for the complexity and cost of scaling. While he notes that EUV challenges have moved beyond physical principals to engineering issues that are now solvable, he says manufacturing EUV tools is not a profitable business, noting that ASML is the only company that has the capability, and even though device makers paid for tool development, the company takes a loss on the tools. Similarly, he says EUV photoresists are also a loss leader. Because of this, Merck focuses efforts on the development of EUV support materials, such as rinses, as well as directed self-assembly (DSA) for alternative approaches to lithography. On the advanced packaging side, the company develops lead-free solder replacements and conductive pastes for die-attach.

Brewer Science, however, is not ready to give up on EUV entirely and is hedging its bets by developing both EUV photoresists that enable 3nm nodes, as well as DSA materials that form the lithography patterning without a photo imaging step. Ram Trichur, Brewer Science, explained that while DSA is still in development, it will allow scaling to reach <3nm nodes. Additionally, the company has a robust temporary bond/debond portfolio to support all system-in-package (SiP), package on package (PoP), interposer integration and 3D TSV processes.

“We need to focus on both the front and back end, because dimensional scaling is continuing, and we believe both EUV and DSA will play an important role,” said Trichur. “However, we also think there are more gains to be made in heterogeneous integration because it hasn’t been used to its fullest potential yet.”

“Even though EUV will happen now, it’s slower than imagined. Continued dimensional scaling boils down to the cost of EUV. Challenges of continued shrink are so Herculean that it’s inevitable that things will move to the 3rd dimension. Additionally, WLP represents relaxation in the ground rules in a regime where we know how to play.” said Jim O’Neill, Entegris. Ultimately, he says it’s a cost trade-off between 3D and EUV that will be decided based on the target applications.

On the other hand, Bill Suber, Reno, says he sees plenty of opportunities still tied to dimensional scaling and the need for plasma based processes. “Leading etch and deposition tool companies are shipping thousands of chambers. Three or four leading-edge companies are enough to drive our business,” he said. “additionally, there is a large install base of older generation tools that need upgrading. We see huge growth potential for us going forward.”

The Impact on Tool Suppliers
Not surprisingly, the establishment of the Heterogeneous Integration Roadmap has been great news for the companies who took the risk early on and built businesses to support it long before the roadmap existed.

“Moore’s law allowed the industry to ignore advanced packaging from a performance perspective. It (packaging) was an after-thought,” noted Craig Mitchell, Invensas, a subsidiary of Xperi. “As it becomes more difficult to scale process nodes, the packaging is the new knob people are leveraging. The old way isn’t doing it anymore, and we are feeling a strong pull for our Zibond™ and DBI™ 3D interconnect technologies.”

Markus Wimplinger, EV Group, says the company is seeing interest from IDMS and OEM for their wafer bonding systems and supporting technologies that the outsourced semiconductor and test service (OSAT) providers already have. The company spent the last ten years providing process services and helping companies develop process flows, sharing its knowledge to help customers implement the best solutions.

“For us, it confirms our strategy was right and has opened new opportunities for us,” said Wimplinger. “We have to ensure we are prepared to respond to increasing needs of our customers and support them on their journey to high volume manufacturing. To do that, we will continue innovating. We can never lean back and be too self-confident. Rather, we need to look forward three to five years and develop those solutions.”

“Heterogeneous integration is a new name for something that has always existed for people coming from the back-end,” said Gilles Fresquet, CEO, UnitySC. “Our position has always been to support ‘more than Moore’. We are not targeting scaling markets. Eight years ago, we decided to focus on 3D TSVs, and then FOWLP, and have seen growth based on process integration adoption. come from heterogeneous integration.”

Rezwan Lateef, Ultratech, attributes the current growth in the advanced packaging market, particularly FOWLP, as a replacement for more costly interposer technologies. He noted that Ultratech has experienced an increase it’s lithography stepper sales that can be directly related to the increase in RDL layers for advanced FO technologies.

Should Tools for Heterogeneous Integration Cost Less?
One of the challenges facing tool manufacturers that target the heterogeneous integration market is the expectation that these tools should cost less than those targeting front-end processes. This is primarily because they were traditionally purchased for OSATs, who have a significantly lower profit margin than foundries. But now, IDMs like Intel are demanding wafer-level processing tools

that achieve dimensions (below 1µm l/s) and smaller bump pitches are demanding that these tools be made available at a much lower cost than tools for the front end.

“Why?” asks Yann Guillou, UnitySC. “The value of the wafer is higher at the end of the process than it is at the beginning. Why should we have tools that are lower cost than a front-end tool? Why should the equipment be cheaper for the back-end than the front end for companies like Intel, when the final outcome is a wafer that has a higher value? IDMs should be ready to pay the price.”

Why indeed? Regardless of whether these tools are being sold to foundries, OSATS or IDMS, at the end of the day, the devices they enable have a higher value than previous generation devices.  Clearly, to deliver end-user products at a price the market can bear, there needs to be a redistribution of profit margin throughout the supply chain so that all stand to benefit. When, if, and how that resolves, remains to be seen. ~ F.v.T.

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